Static random access memories (SRAMs) include columns and rows of storage cells, each including a circuit with transistors. Existing six-transistor (6T) SRAM architecture has a 12 unit2 of bitcell area, which needs to be further reduced as technology progresses further into the advanced technology nodes. There is a design requirement to form a large number of memory cells on a chip of reasonable size, while at the same time reducing memory cell size and increasing integration density to minimize resistance and capacitance of transistors and connections in order to improve performance. SRAM cell designs can use FinFETs in which the conduction channel is a raised, fin-like structure. This design permits the gate to be placed on two or more sides of the channel to improve conduction and leakage control.
A need therefore exists for methodology enabling the formation of memory structures using FinFETs with reduced bitcell area layout, and a resulting device.